1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to a technique of monitoring and testing the reliability of circuit elements, such as field effect transistors, with respect to the lifetime of these elements.
2. Description of the Related Art
In modern integrated circuits, feature sizes of individual circuit elements, such as transistors, resistors, capacitors and the like, are steadily decreased to improve the device performance in terms of operational speed and/or power consumption. The continuous reduction in size of the circuit elements, however, is usually not a straightforward development and may require significant effort in adapting process techniques to achieve the target design dimensions. Additionally, the shrinkage of certain circuit elements or parts thereof usually entails a corresponding scaling of other circuit parts, thereby creating a plurality of issues that have to be dealt with. For example, the continual reduction of the channel length of field effect transistors, i.e., the distance between the source and the drain region of the transistor, typically requires the gate insulation layer, i.e., the dielectric layer electrically insulating the gate electrode from an underlying channel region, to be reduced in thickness so as to produce the necessary capacitive coupling between the gate electrode and the channel region as is required for proper control of the transistor function.
Currently, integrated circuits such as CPUs are fabricated on the basis of CMOS technology, producing transistors having a gate length in the range of approximately 0.1 μm and less. The devices having a channel length on this order of magnitude may require a gate insulation layer having a thickness of 2–3 nm when the dielectric material is silicon dioxide, possibly including a certain amount of nitrogen. For further device scaling, the thickness of silicon dioxide based gate insulation layers may even require dimensions that are significantly less than the above-specified range. As a consequence, the formation of ultra-thin gate insulation layers having reliable and predictable characteristics over a specified lifetime of the circuit element under consideration is a challenging task for semiconductor manufacturers. Although alternative materials and process techniques for manufacturing gate insulation layers appropriate for extremely scaled transistor devices have been proposed, it is nevertheless essential that the characteristics of the gate insulation layer be thoroughly monitored so as to be able to comply with product specifications established for a certain type of product.
In addition to the gate insulation layer thickness, other parameters, such as gate dopant concentration and well dopant concentration, also have a tremendous impact on the finally achieved dielectric breakdown of a transistor element and, thus, on the reliability and expected lifetime of the entire integrated circuit. Reliability is important because the failure of a single transistor element may cause a catastrophic failure of the entire device. For this reason, monitoring the time to dielectric breakdown of selected transistor elements has become a standard means for monitoring and assessing the reliability of gate dielectrics used in gate insulation layers. A meaningful accurate reliability assessment, however, requires the availability of a sufficient number of test devices to allow a quantitatively well-based statement on the expected lifetime of the devices. Consequently, multiple test structures are required on every product wafer so as to reliably estimate and assess the time to dielectric breakdown of the test devices. As previously pointed out, in manufacturing high performance integrated circuits, process amendments for optimizing and adapting process parameters are frequently necessary and even further emphasize the necessity for accurate reliability assessments, since at least some of the process changes may potentially impact the reliability of the devices.
With reference to FIGS. 1a–1d, a conventional test structure as is implemented in large numbers on a product substrate will now be described in more detail. FIG. 1a schematically shows a cross-sectional view of an integrated transistor test structure that enables the monitoring of the time to dielectric breakdown of a single transistor device formed in accordance with a specific type of transistor as also used on product areas of the substrate. A test structure 100 comprises a substrate 101, for example a silicon substrate, in which a lightly doped semiconductor region 102 is formed, which is hereinafter referred to as the “well region.” Moreover, in the example, an N-channel transistor will be described and, therefore, the well region 102 is provided as a P-well region. A trench isolation structure 103 formed in the substrate 101 separates a well contact 110 and a transistor structure 120 from each other. The well contact 110 comprises a highly doped semiconductor layer 111 that acts as an electrode for electrically connecting to the well region 102.
The transistor structure 120 comprises highly doped source and drain regions 121, which are separated by a channel region 122 that forms a conductive channel upon application of an appropriate voltage to a gate electrode 123. The gate electrode 123 may be comprised of any appropriate conductive material and may, according to sophisticated CMOS techniques, comprise highly doped polysilicon. Since the transistor structure 120 is to represent an N-channel transistor, the source and drain regions 121 and the gate electrode 123 may be doped by N-type dopants. Sidewall spacers 125 may be formed on sidewalls of the gate electrode 123 and a gate insulation layer 124 separates the channel region 122 from the gate electrode 123. As previously noted, the gate insulation layer 124 may be of a complex structure, i.e., may include various materials having a high permittivity, and/or may have an extremely small thickness of 2 nm and even less. Consequently, any variations during manufacturing of the gate insulation layer 124, variations of the dopant concentrations of the gate electrode 123 and of the well region 102, the dopant profile of which may require a complex succession of implantation sequences, and variations during operation of the device may lead to significant variations in the lifetime of the gate insulation layer 124.
Furthermore, for the sake of simplicity, other components of the test structure 100, such as silicide regions formed in the drain and source regions 121 and the gate electrode 123, as well as contact plugs formed on the drain and source regions 121, the gate electrode 123 and the well contact 110, are not shown in FIG. 1a so as to not unduly obscure the principals of the test structure 100. Furthermore, any metallization layers, i.e., layers including conductive vias and lines for interconnecting individual circuit elements, are not shown in FIG. 1a but may form a part of the test structure 100.
FIG. 1b schematically shows a top view of the structure 100 with contact plugs 126 for connecting to the source and drain region 121, contact plugs 127 connecting to the gate electrode 123, and contact plugs 128 connecting to the well contact 110. The contact plugs 126 may finally be connected to a metal pad formed on top of the final metallization layer (not shown), wherein the total number of metallization layers may depend on the specific design of the test structure 100. Since typically the test structure 100 is formed on a product substrate 101, the test structure 100 is commonly manufactured with the devices on the product chip areas. Accordingly, the design and the number of the metallization layers are dictated by the product chips formed on the substrate 101. For convenience, the metal pad connected to the contact plugs 126 may be referred to as pad 1 and may have dimensions that allow contact of the pad 1 by an appropriate electrode of a test tool. Similarly, the contact plugs 127 are finally connected to a further metal pad, referred to as pad 2, and the contact plugs 128 are connected to a third metal pad, referred to as pad 3.
Again referring to FIG. 1a, the combination of contact plugs and conductive lines formed in any metallization layer, and the corresponding metal pads 1, 2 and 3 may be illustrated in FIG. 1a in a simplified manner and may be indicated as terminals p1, p2 and p3, respectively. Thus, p1 represents an electrical connection from the drain and source regions to the metal pad 1, wherein, for example, an electrical connection between the two drain and source regions 121 may be established in the first metallization layer and a single connection may then be formed from the metallization layer 1 to the contact pad 1. Similarly, the terminal p2 represents the electrical connection from the gate electrode 123 to the metal pad 2, and the terminal p3 represents the electrical connection from the well contact 110 to the metal pad 3.
A typical process flow for forming the test structure 100 as shown in FIG. 1a may comprise conventional and well-established manufacturing processes to form the transistor structure 120 and the well contact 110. Thus, a detailed description thereof is omitted herein. After completion of the transistor structure 120 and the well contact 110, as illustrated in a simplified manner in FIG. 1a, one or more metallization layers may be formed in accordance with well-established process steps wherein, for instance, the source and drain regions 121 are shorted by a corresponding metal line (not shown). Thereafter, the one or more metallization layers are completed and the metal pads 1, 2 and 3 are formed so as to be accessible by a test device. It should be noted that the dimensions of the metal pads 1, 2 and 3 are significantly larger than those of the associated test structure 100 and therefore a large amount of valuable chip area is consumed by the metal pads 1, 2 and 3.
During operation, a ground potential is applied to the terminals p1 and p3, that is, to the contact pads 1 and 3, whereas a positive voltage is applied to terminal p2 with a magnitude that insures the formation of an inversion channel in the channel region 122. Usually, the voltage applied to the terminal p2 and thus to the gate electrode 123 is significantly increased compared to normal operation conditions to reduce the time required for occurrence of electrical breakdown events. During application of the gate voltage, the environmental conditions of the test structure 100 may be chosen so as to resemble typical environmental conditions during operation of the semiconductor device under consideration. While applying the gate voltage to the gate electrode 123, the leakage current flowing from the gate electrode 123 into the channel region 122 is steadily monitored. Upon occurrence of a dielectric breakdown, the leakage current significantly increases and the time interval may be used to assess the lifetime of the actual device under consideration.
FIG. 1c schematically shows a graph representing the gate leakage current indicated as Ig versus the time of application of the gate voltage. As is shown, at time point Tf, an electrical breakdown of the gate insulation layer 124 occurs and consequently a significantly higher leakage current Ig is drawn.
As previously pointed out, a plurality of test structures 100 is typically required for a specific type of circuit element to be tested in order to be able to carry out a thorough analysis and to obtain meaningful statistical results. Consequently, approximately 30–100 test structures 100 are usually provided for a specified type of circuit element, thereby requiring thrice a certain number of metal pads 1, 2 and 3. As these metal pads consume significant chip area owing to the relatively large dimensions thereof, only a reduced number of saleable products may be formed on the substrate 101.
In view of the above-identified problems, a need exists to provide a technique for monitoring electrical breakdown events on a substrate with required statistical relevance while reducing the floor space consumed by respective test structures.